(1) Field of the Invention
The present invention relates to a processor and a compiler therefor, in particular, to a very-long instruction word (VLIW) processor and the like which simultaneously execute a plurality of instructions.
(2) Description of the Related Art
Conventionally various kinds of VLIW processors have been suggested, said VLIW processors comprising a plurality of executing units and executing a plurality of instructions included in a very long instruction word in each clock cycle (for example, refer to Japanese Laid-Open Patent publication No. 2004-005733).
FIG. 15A is a diagram showing an example of an instruction format of a very long instruction word which a conventional VLIW processor executes. Here, a very long instruction word is shown, said word including three instruction fields where the three instructions #1-#3 which can be executed in parallel are placed. Each instruction field has, in the case of a register operation instruction, an operational code which indicates the kind of the operation and an operand which indicates the subject of the operation (for example, a register specifying area operable to specify two source registers src1 and src2 and one destination register dst).
FIG. 15B is a diagram showing an example of an architecture (here, an architecture focusing on the input/output of the register) of the conventional VLIW processor which executes the very long instruction word as described above. Here, the architecture which includes a register file and three operation units is shown.
According to the conventional VLIW processor described above, for example, register operation instructions are simultaneously executed up to the maximum of three, and a faster processing has been developed, said register operation instructions calculating the values stored in two registers and storing the result in one register.
However, as shown in FIG. 15A, the very long instruction word of the conventional VLIW processor has register specifying areas up to the maximum of three (src1, src2 and dst) for each instruction field. Thus, there is a problem that the total number of bits of the register specifying area(s) which is (are) included in one very long instruction word becomes very large.
For example, a VLIW processor which comprises a register file including 32 registers requires 5 bits to specify one register. Thereby, the instruction format as shown in FIG. 15A requires the maximum of 15 bits of register specifying areas for each instruction field, that is, the maximum of 45 bits of register specifying areas for the whole very long instruction word. As a result, the circuit size related to the instruction path of the VLIW processor becomes large.
Moreover, according to the instruction format as shown in FIG. 15A, the number of registers simultaneously connected to the input ports of the operation units is 6 at the maximum. Therefore, as shown in FIG. 15B, 6 output ports are necessary for the register file. In this point, as well, there is a problem that the circuit size becomes large.